1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device including a fuse unit.
2. Description of the Related Art
In general, a semiconductor device such as DRAM (Dynamic Random Access Memory) includes a fuse circuit. The fuse circuit is a circuit that inverts and outputs a previous option signal through a fuse programming method, and it is used in a voltage control circuit, a redundancy circuit or the like to selectively provide an option signal.
In general, the fuse programming method may include a laser blowing method and an electrical method. The laser blowing method is to cut off the connection state of a fuse using laser beams. The fuse programming method using laser beams may be performed only in a wafer state before a semiconductor device is fabricated into a package. On the other hand, the electrical method is to program a fuse by changing the connection state of the fuse in a package state of semiconductor device fabrication. At this time, an anti-fuse may be used as the fuse.
The anti-fuse has an opposite concept to a prevalent fuse. Specifically, the anti-fuse is set to be cut off at the initial stage of semiconductor device fabrication, and then it is switched to a connection state by a program operation after packaging. In other words, the anti-fuse at the initial stage of fabrication is maintained as an insulator having a high resistance of MΩ or more, but it is then changed into a conductor having a low resistance of several hundred Ω or less depending on a program operation. Here, the physical change of the anti-fuse is performed as follows. When a voltage having a given level or more is applied between two conductive layers of the anti-fuse to break down insulation characteristics, the anti-fuse is switched into a conductor.
FIG. 1 is a configuration diagram of a conventional anti-fuse circuit.
Referring to FIG. 1, the anti-fuse circuit 10 includes an anti-fuse 12 and an output unit 14. The anti-fuse 12 is configured to be programmed when a voltage difference equal to or more than a critical value occurs between both ends thereof. The output unit 14 is configured to output a fuse information signal SA corresponding to a rupture state of the anti-fuse 12.
Here, the anti-fuse 12 includes an NMOR transistor N1 having a gate terminal configured to receive a selectively-provided power supply voltage VDD and source and drain terminals connected to a detection node ND1.
The output unit 14 includes a resistor 14A and a sense amplifier 14B. The resistor 14A is connected between the detection node ND1 and a ground voltage terminal VSS, and the sense amplifier 14B is connected to the detection node ND1 and configured to amplify the voltage level of the detection node ND1 and output the fuse information signal SA.
Hereinafter, an operation of the anti-fuse circuit 10 having the above-described configuration will be described with reference to FIGS. 2A and 2B.
FIG. 2A illustrates an equivalent circuit of the anti-fuse circuit which is not programmed. FIG. 2B illustrates an equivalent circuit of the anti-fuse circuit 10 which is programmed.
First, referring to FIG. 2A, since the power supply voltage VDD is not supplied when program is not performed (floating state), the anti-fuse 12 is not broken down. That is, the current state of the anti-fuse does not satisfy a condition for applying stress, corresponding to such a level as to program the anti-fuse 12, to both ends of the anti-fuse 12. Accordingly, since the anti-fuse 12 operates as a capacitor C1, the anti-fuse 12 is maintained as an insulator having a high resistance. Therefore, the detection node ND1 is connected to the ground voltage VSS, and the sense amplifier 14B outputs the fuse information signal SA of a logic low level.
On the other hand, referring to FIG. 2B, since the power supply voltage VDD is supplied when program is performed, the current state satisfies the condition where the anti-fuse 12 is programmed. That is, since a voltage difference corresponding to such a level as to program the anti-fuse 12 may occur between both ends of the anti-fuse 12, the anti-fuse 12 may be broken down. Accordingly, since the anti-fuse 12 operates as a resistor R2, the anti-fuse 12 is switched to a conductor having a low resistance. Therefore, the detection node ND1 has a voltage level between the power supply voltage VDD and the ground voltage VSS, the sense amplifier 14B outputs the fuse information signal SA of a logic high level.